Recently prevalent, portable wireless communication terminals have been desired to exhibit faster processing speed, and a PLL (phase locked loop) circuit that operates at a high frequency band is indispensable as a frequency synthesizer to wireless communication.
The PLL circuit has a configuration including a frequency divider that subjects a high frequency band signal to a low frequency band signal by means of frequency division. An injection locked frequency divider (ILFD) capable of high speed operation at a very high frequency band of 10 GHz or more is used as a frequency divider.
The injection locked frequency divider has a narrow locking range (an operation band). In order to activate the injection locked frequency divider over a wide frequency band, a calibration method for controlling the lock range in agreement with a desired frequency has been required (see; for instance, Patent Literature 1).
FIG. 10 is a circuit diagram of a PLL circuit using a related art injection locked frequency divider described in connection with Patent Literature 1. FIG. 11 is a flowchart for describing calibration of the PLL circuit using the related art injection locked frequency divider described in connection with Patent Literature 1.
As shown in FIG. 10, a PLL circuit 100 includes a voltage controlled oscillator (VCO) 101, an injection locked frequency divider 103, a frequency divider 105, a phase frequency detector+charge pump 108, a loop filter 110, a calibration circuit 114, and a lookup table 115. The voltage controlled oscillator is hereunder abbreviated simply as VCO.
In the PLL circuit 100, an output signal 102 derived by oscillation of the VCO 101 is injected (input) to the injection locked frequency divider 103, where the signal is frequency-divided up to a low frequency signal 104 of the order of 10 GHz. The frequency signal 104 is input to the frequency divider 105, where the frequency signal is frequency-divided to a frequency of a reference signal 107 by the frequency divider 105.
The phase frequency detector+charge pump 108 compares a signal (a frequency-divided signal 106) output from the frequency divider 105 with the reference signal 107, converting a component of an error between a phase and a frequency into an electric current 109. The electric current 109 is input to the loop filter 110. In accordance with the input electric current 109, the loop filter 110 generates a control voltage 112 for the VCO 101.
The VCO 101 is controlled by the control voltage 112, thereby diminishing the error detected by the phase frequency detector+charge pump 108. The PLL circuit 100 thereby operates as a circuit that performs frequency negative feedback operation.
The calibration circuit 114 adjusts (calibrates) a control value of a control signal 113 for the injection locked frequency divider 103 at an oscillation band of the VCO 101 by use of the reference signal 107 and the frequency-divided signal 106 from the frequency divider 105. By means of the control signal 113, the injection locked frequency divider 103 can operate in a vicinity of the center of the locking range of the injection locked frequency divider 103.
Calibration procedures of the PLL circuit 100 are described by reference to FIGS. 10 and 11.
The calibration circuit 114 selects an oscillation band of the VCO 101 by use of a band selection signal 111 (S200). The band selection signal 111 is output from the calibration circuit 114.
The calibration circuit 114 sets the control voltage 112 of the VCO 101 (S202). For instance, the calibration circuit 114 sets a predetermined value (e.g., Vdd/2) as the control voltage 112.
The calibration circuit 114 measures a frequency of the frequency-divided signal 106 when a change occurs in the control value of the control signal 113 for the injection locked frequency divider 103 (S204).
The calibration circuit 114 calculates a difference between a variation in control value of the control signal 113 of the injection locked frequency divider 103 and a variation in frequency of the frequency-divided signal 106 (S206).
On the basis of a calculation result yielded in step S206, the calibration circuit 114 specifies a locking range of the injection locked frequency divider 103 with respect to an oscillation band of the VCO 101 selected in step S200 (S208).
On the basis of an ascertainment result yielded in step S208, the calibration circuit 114 selects, at the selected oscillation band of the VCO 101, a control value of the control signal 113 by means of which the injection locked frequency divider 103 can operate in the vicinity of the center of the locking range of itself (S210). The calibration circuit 114 stores the control value of the control signal 113 selected in step S210 in the lookup table 115.
The calibration circuit 114 selects another oscillation band in the VCO 101 and repeats operation from steps S202 to S210 (S212). The PLL circuit 100 can store the control value of the optimum control signal 113 of the injection locked frequency divider 103 to each of the oscillation bands of the VCO 101 into the lookup table 115.